1. Field
The present invention relates generally to signal processing and, more particularly, to digital to analog conversion.
2. Description of Related Art
One of the major limitations in high fidelity low power audio design, such as for headsets, is thermal noise of the DAC components. In a typical DAC design, thermal noise is a fixed value once the maximum output voltage and load requirements are determined DAC output referred thermal noise at the driver output does not change even if the signal swing is reduced. Because of this, in order to provide acceptable idle channel noise characteristics, the DAC device is usually relatively large that leads to inefficient use of chip space and high power consumption.
One attempt at a solution is to provide a three-level digital-to-analog converter using both PMOS and NMOS devices as matched current courses. However, this solution introduces a number of issues. For example, there must be almost perfect matching between each PMOS device and its corresponding NMOS device. Mismatch between PMOS and NMOS devices creates significant linearity issues that affect the overall chain and the subsequent amplifier design. Additionally, using NMOS devices makes it more difficult to isolate noise.
Digital-to-analog converters can be used in an open-loop configuration and can also be used in the feedback loop of a sigma-delta converter. One existing discrete-time second-order order delta-sigma ADC design is the active-passive delta-sigma modulation (APDSM) ADC. APSDM ADCs are subject to resistor and capacitor absolute value variances and excess loop delay and parasitic poles. Variances in resistor and capacitor absolute value tend to cause large absolute ADC gain variations and the movement of poles and zeros, which degrades performance and stability. Counteracting these vulnerabilities requires extra circuitry to control the reference voltage so that the absolute gain of the ADC does not vary substantially. Excess loop delay and parasitic poles vulnerabilities require the amplifier, comparator, and DAC to meet delay requirements over an expected range of frequencies. Further, a loop delay compensation circuit may be required to reduce sensitivity to quantizer metastability, latch clock-to-Q time, and feedback DAC propagation delay. Also, APSDM ADCs may require that the input common mode voltage be level-shifted for proper operation and reliability. This requires additional circuits for level-shifting, which consume additional chip area and power.
In addition to the design constraints mentioned above, in a typical, existing second-order sigma-delta APSDMs, the feedback DAC is a single bit DAC. This single bit DAC is switched so as to be connected to the plus and minus sides of the input for half of a given time period. Thus, the value of the common mode bleed resistors are chosen to provide a desired common mode voltage drop when a current (IDAC/2) passes through each bleed resistor. The undesired result is that the noise of the first stage integrator (passive) is referred back to the input stage and, as a result, amplified. Thus, the noise floor of the APSDM is limited.
There remains a need for an improved architecture for a three-level digital-to-analog converter that addresses at least some of the shortcomings of the current architectures described above.